Clock signals are used to synchronize the flow of data signals among synchronous signal paths. In some applications, clock signals control the command signals sent to interconnected digital blocks within a system. Such applications may include a clock distribution system providing a variety of clock frequencies with high precision, low noise, and predictable phase alignment.
Phase-locked loops (PLLs) can be implemented in a clock distribution system. A PLL is a closed loop system for locking the phase of a reference clock with an oscillator. A PLL can be designed to be of a specific type (e.g., type-I, type-II, or higher) with a specific order (e.g., 1st order, 2nd order, or higher). In system theory, the type can refer to the number of integrators within the loop and the order can refer to the degree of the denominator in the PLL system transfer function. In some applications, a clock distribution system can use a single clock source as an input and generate multiple clock outputs with a frequency that is different compared to the single clock source.